1. Field of the Invention
The present invention relates generally to decimators, i.e., electrical circuits operative to reduce by a certain factor the sampling rate of a sampled input signal having a given input sampling frequency. In particular, the invention relates to the implementation of decimators by the use of finite impulse response (FIR) digital filters.
2. Description of the Prior Art
It is known generally that decimators may be implemented by the use of FIR filters. The subject is discussed in several recent publications. For example, see "Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-Band Filtering," by R. E. Crochiere, et al., IEEE Trans. Accoustics, Speech, & Signal Processing (vol. ASSP-23, October 1975); "Further Considerations in the Design of Decimators and Interpolators," Id. (vol. ASSP-24, August 1976); and "Interpolation and Decimation of Digital Signals--A Tutorial Review," Proc. IEEE (vol. 69, March 1981). The contents of the foregoing articles are incorporated by reference herein.
A conventional K to 1 decimator, where K is the decimation factor, may be realized by using an FIR filter having a length N where N&gt;K. It will be understood that as an input sample x(n) progresses through the filter, it will be multiplied by N/K different coefficients and will get accumulated N/K times. A simple way to describe the operation is by following a sample through such a filter.
Assume that an output sample was generated and a new input sample x(1) arrives at the input of the filter. Since the filter is used as a decimator, one output is computed for every K input samples. The sample x(1) is, therefore, shifted into a delay line and is not multiplied or accumulated until K cycles later. At that time, the sample x(1) is multiplied by the Kth coefficient, a(K), and accumulated. Another K cycles later, the same sample is multiplied by a(2K) and the process is repeated N/K times, whereupon the sample is shifted out of the filter.
In the conventional N-tap FIR filter-implemented decimator, therefore, the filter requires N memory locations regardless of the decimation factor K. Such memory requirement, together with a controller capable of carrying out the necessary memory addressing, can be quite costly.
It is also possible to use a known polyphase implementation as shown in FIG. 1, which requires K branches with N/K delays each. Such implementation, obviously, does not change the memory requirements or the complexity of addressing the memory.